View SAA2510_1182938.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAA2510 Video CD (VCD) decoder
Preliminary specification File under Integrated Circuits, IC02 1996 May 21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
FEATURES (With standard microcode loaded) * Decoding and display of MPEG1 video streams (constrained parameters) * Decoding of MPEG audio streams (layer II) * Decoding, storage (compressed) and display of high-resolution still pictures of 704 x 576 pixels * Requires only 4 Mbits of external 70 ns DRAM * Audio transparency mode for CD-DA discs * On-screen display capability * Play options: - Play - Stop - Pause/continue - Slow-motion forward - Scan forward - Scan backward. * Supports auto-pause feature * Disc interface: Philips I2S, EIAJ, MEC formats and IEC 958 (EBU) interface * Separate error flag input (EFIN) and data valid input (NDAV) * Performs basic block decoder functions: - serial-to-parallel conversion - sync detection - descrambling - EDC calculation - error-correction for mode 2 form 1 sectors - header and sub-header interpretation. * I2C-bus interface * Video output YUV 4 : 2 : 2 format. DMSD bus compatible * Also supports CCIR656 video interface, including line and field timing codes * Audio output: 44.1 kHz. 16, 18 or 20 bits per audio sample in Philips I2S, Sony or MEC formats ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA2510 QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height 2 APPLICATION * Dedicated video CD players. GENERAL DESCRIPTION
SAA2510
* EBU audio output, fully transparent from input to output in CD-DA mode and generated in MPEG mode * Downloadable microcode for internal controllers * Internal video timing generator * Requires 40 MHz crystal for system clock generation * Requires 27 MHz crystal or external 27 MHz source for video timing generation * Requires 16.9344 MHz (384 x 44.1 kHz) clock locked to CD drive * Internal generation of 90 kHz MPEG clock * Capability of sharing external DRAM by 3-stating all DRAM pins.
MPEG1 audio and video CD (VCD) decoder, intended for use in low-cost dedicated video CD players. When used with a 4 Mbit DRAM and a digital video encoder, the decoder adds the required functionality to a CD decoder to implement a low-cost video CD player capable of playing discs coded to version 2.0 of the video CD specification. The SAA2510 is an I2C-bus controlled chip and features serial data input in four common bus formats. It provides digital video output in CCIR601 and 656 formats. A bit-mapped on-screen display is provided and output video timing can be 525 lines/30 frames per second or 625 lines/25 frames per second. The chip is microcode programmable for feature enhancement.
VERSION SOT317-1
1996 May 21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
QUICK REFERENCE DATA SYMBOL VDD3 VDD5 IDD fxtal s fxtal v fi Tamb PARAMETER supply voltage supply voltage supply current system clock crystal frequency video clock crystal frequency audio clock input frequency operating ambient temperature MIN. 3.0 4.5 - - - - -20 3.3 5.0 tbf 40.0 27.0 16.9344 - TYP.
SAA2510
MAX. 3.6 5.5 - - - - +70 V V
UNIT
mA MHz MHz MHz C
1996 May 21
3
andbook, full pagewidth
1996 May 21
EXTERNAL 4 Mbit DRAM OSD BUFFER 3k PLAY CONTROL BUFFER 7k Sys_osc_1 76 Sys_osc_0 74 RESET 27 W SYSTEM CLOCK EBUIN AUDIOCLK WSIN CLIN EFIN DAIN NDAV SDA SCL INT ASEL HOST I2C INTERFACE SYSTEM CONTROLLER BLOCK DECODER
BLOCK DIAGRAM
Philips Semiconductors
Video CD (VCD) decoder
AUDIO FIFO
VIDEO FIFO
VIDEO BUFFER 0
VIDEO BUFFER 1
VIDEO BUFFER 2
CAS RAS A0 to A8
CDIR DR0 to DR15 79 84
MEMORY MANAGEMENT UNIT VIDEO CLOCK
86 82 80
Vid_osc_0 Vid_osc_1 CLK27 CREF
VIDEO DECODER 8 8 DATA SORTER IDCT FRAME RECONSTRUCTOR VIDEO GENERATOR
7 to 1 100 95 to 88 99 97 11 9
UV0 to UV7 Y0 to Y7 VSYNC HREF TLSAND CSYNC
4
SAA2510
AUDIO DECODER TEST CONTROL 77 TP1 78 TP2 28
12 13 16 14
EBUOUT DAOUT CLOUT WSOUT
Preliminary specification
MGE325
DRAMON
SAA2510
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
PINNING SYMBOL UV6 PIN 1 video UV bus output bit 6; DESCRIPTION
SAA2510
16-bit video output mode: the UV bus outputs alternating U and V chroma samples at 13.5 Mbytes/s CCIR656 mode: this bus is not used (inactive) UV5 UV4 UV3 UV2 UV1 UV0 VDD5 CSYNC VSS5 TLSAND EBUOUT DAOUT WSOUT VDD3 CLOUT VSS AUDIOCLK VDD5 EBUIN CLIN WSIN DAIN VDD3 EFIN VSS RESET DRAMON INT NDAV ASEL SDA VDD5 SCL VSS5 DR15 1996 May 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 video UV bus bit 5 video UV bus bit 4 video UV bus bit 3 video UV bus bit 2 video UV bus bit 1 video UV bus bit 0 5 V external pad power supply composite sync output; 525 lines/60 Hz or 625 lines/50 Hz 0 V external pad power supply two-level Sandcastle (composite blanking) output; requires external resistor network to define horizontal/vertical blanking level IEC 958 digital audio output I2S data; digital audio output I2S word select digital audio output +3 V internal power supply I2S bit clock output 0 V internal power supply 16.9 MHz audio clock input 5 V internal power supply EBU (IEC 958) input I2S bit clock input I2S word select input I2S digital data input +3 V internal power supply error flag input from I2S source 0 V internal power supply active low reset input DRAM pin 3-state control input; also 3-states video outputs and some timing signals active low open drain interrupt request to host microcontroller data not valid input (data on I2S or EBU input not valid) I2C-bus address select pin I2C-bus data pin 5 V external pad power supply I2C-bus clock input 0 V external pad power supply DRAM data input/output bit 5 5
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL DR14 DR13 DR12 DR11 DR10 DR9 VDD5 DR8 VSS5 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 VSS5 CAS VDD5 A8 A7 A6 A5 A4 VDD3 W VSS RAS VDD5 A3 VSS5 A2 VDD5 A1 A0 VDDO3 Sys_osc_0 VSS Sys_osc_1 TP1 1996 May 21
PIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 DRAM data input/output bit 14 DRAM data input/output bit 13 DRAM data input/output bit 12 DRAM data input/output bit 11 DRAM data input/output bit 10 DRAM data input/output bit 9 5 V external pad power supply DRAM data input/output bit 8 0 V external pad power supply DRAM data input/output bit 7 DRAM data input/output bit 6 DRAM data input/output bit 5 DRAM data input/output bit 4 DRAM data input/output bit 3 DRAM data input/output bit 2 DRAM data input/output bit 1 DRAM data input/output bit 0 0 V external pad power supply DRAM column address strobe 5 V external pad power supply DRAM row/column address pin A8 DRAM row/column address pin A7 DRAM row/column address pin A6 DRAM row/column address pin A5 DRAM row/column address pin A4 +3 V internal power supply active low DRAM write strobe 0 V internal power supply DRAM row address strobe 5 V internal power supply DRAM row/column address pin A3 0 V external pad power supply DRAM row/column address pin A2 5 V external pad power supply DRAM row/column address pin A1 DRAM row/column address pin A0
DESCRIPTION
3 V internal power supply for oscillator oscillator input pin; 40 MHz oscillator 0 V internal power supply oscillator output pin; 40 MHz oscillator factory test pin; connect to ground 6
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL TP2 CDIR CREF VSS5 CLK27 VDD5 Vid_osc_0 VSS Vid_osc_1 VDDO3 Y7
PIN 78 79 80 81 82 83 84 85 86 87 88 factory test pin; connect to ground
DESCRIPTION clock direction control pin; when high, CLK27 is an output clock qualifier output; 13.5 MHz timing signal used in 16-bit video output mode; can also be used as 13.5 MHz video sample clock 0 V external pad power supply 27 MHz clock input or output; direction controlled by CDIR pin 5 V external pad power supply oscillator pin; 27 MHz; input pin 0 V internal power supply oscillator pin; 27 MHz; output pin 3 V internal power supply for oscillator video Y bus output bit 7 DMSD mode: the Y bus outputs luminance samples at 13.5 Mbytes/s CCIR656 mode: this pin supplies multiplexed chrominance and luminance (27 Mbytes/s)
Y6 Y5 Y4 Y3 Y2 Y1 Y0 VSS5 HREF VDD5 VSYNC UV7
89 90 91 92 93 94 95 96 97 98 99 100
video Y bus bit 6 video Y bus bit 5 video Y bus bit 4 video Y bus bit 3 video Y bus bit 2 video Y bus bit 1 video Y bus bit 0 0 V external pad power supply horizontal (line) timing reference signal; high during active video part of line, low during line blanking 5 V external pad power supply vertical (field/frame) timing reference signal; high during vertical blanking interval of field video UV bus output bit 7 DMSD mode: the UV bus outputs alternating U and V chroma samples at 13.5 Mbytes/s CCIR656 mode: this bus is not used (inactive)
1996 May 21
7
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
86 Vid_osc_1
handbook, full pagewidth
85 VSS 84 Vid_osc_0
87 VDDO3
99 VSYNC
83 VDD5 82 CLK27
97 HREF
98 VDD5
96 VSS5
100 UV7
UV6 UV5 UV4 UV3 UV2 UV1 UV0 VDD5 CSYNC
1 2 3 4 5 6 7 8 9
81 VSS5 80 79 78 77 76 75 74 73 72 71 70 69 68 67
95 Y0
94 Y1
93 Y2
92 Y3
91 Y4
90 Y5
89 Y6
88 Y7
CREF CDIR TP2 TP1 Sys_osc_1 VSS Sys_osc_0 VDDO3 A0 A1 VDD5 A2 VSS5 A3 VDD5 RAS VSS W VDD3 A4 A5 A6 A7 A8 VDD5 CAS VSS5 DR0 DR1 DR2
VSS5 10 TLSAND 11 EBUOUT 12 DAOUT 13 WSOUT 14 VDD3 15 CLOUT 16 VSS 17 AUDIOCLK 18 VDD5 19 EBUIN 20 CLIN WSIN DAIN VDD3 EFIN VSS RESET DRAMON INT NDAV 21 22 23 24 25 26 27 28 29 30 ASEL 31 SDA 32 VDD5 33 SCL 34 VSS5 35 DR15 36 DR14 37 DR13 38 DR12 39 DR11 40 DR10 41 DR9 42 VDD5 43 DR8 44 VSS5 45 DR7 46 DR6 47 DR5 48 DR4 49 DR3 50
SAA2510
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
MGE324
Fig.2 Pin configuration.
1996 May 21
8
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
FUNCTIONAL DESCRIPTION Block decoder The VCD chip receives MPEG A/V or CD digital audio data from a CD decoder chipset using any one of four common interface formats (Philips I2S, EIAJ, MEC or IEC 958). The Philips I2S, EIAJ and Matsushita input modes use the bit clock (CLIN), word select (WSIN), data (DAIN) and error flag (EFIN) inputs. If IEC 958 (EBU) input mode is selected, only the EBUIN pin needs to be connected. The chip also requires a 16.9 MHz clock input (CLIN) which is synchronous with the data input from the CD decoder providing the serial data input. The VCD chip contains a block decoder and descrambler which performs error correction on the Video CD data track (form 1) sectors and error detection on real-time audio and video tracks where an error correction code is present. In most events, audio output can be in any of the three (I2S, EIAJ or MEC) formats, independent of input type. When playing CD digital audio discs, the input is copied to the outputs. The block decoder supports some special functions which enable recovery of play control lists. The desired sectors can be acquired by programming a sector address via the I2C-bus microcontroller interface. The microcontroller then instructs the CD servo/decoder subsystem to execute a servo jump to the required disc location and then waits for an interrupt indicating that the desired sector information has been received and error-corrected. System controller Overall control of the chip and a number of its less time-critical functions is carried out by a dedicated RISC processor. The microcode for this processor is executed from an on-chip RAM. This microcode must be loaded into RAM after power-up by the host microcontroller, using the I2C-bus interface. This enables the functionality of the chip to be customized for specific applications. On-screen display The VCD chip provides a bit-mapped On-Screen-Display (OSD), containing 32 display lines of 352 pixels per line. There is a double-height mode which repeats OSD lines so that the maximum height of OSD objects becomes 64 lines. This character-set-independent OSD permits display of ideographic characters and simple graphic displays anywhere on the screen.
SAA2510
The OSD is implemented as 48 vertical `slices' of 8 pixels (horizontally) and 32 (vertically). Each pixel is stored as 2 bits. This gives three programmable logical colours, plus a transparent option. Each slice is identified by a slice code (slice number). The horizontal position of a slice is defined by its position in a slice code sequence written to the VCD chip. This arrangement reduces the need to completely update the OSD bit map in many situations. It may be possible to simply reorder the slices, e.g. if a track time display is being updated and slices are prepared to represent digits. At any time, up to 44 of the 48 slices can be displayed. Video decoder Video output data can be presented in one of two modes: 1. 16-bit wide data is output in YUV 4 : 2 : 2 format as 8 bits of luminance and 8 bits of alternating U and V chrominance. The video output data rate in this mode is 13.5 Mwords/s. 2. 8-bit wide, CCIR656-like, data is output providing 4 : 2 : 2 format video as an 8-bit UYVY multiplex at 27 Mbytes/s. In either case, the VCD chip can be programmed to output 525 line or 625 line format timing to match the type of display (TV) connected to its output. Additional programmability is provided to cope with the Video CD disc source picture coding type (525/625 lines). The VCD chip performs vertical and horizontal interpolation to convert the MPEG SIF (352 pixels per line) normal resolution pictures to CCIR601 resolution. Vertically interpolated pixels are output on the odd fields during display of normal resolution pictures. The Video CD disc being played may have been coded with 525 lines/60 Hz or 625 lines/50 Hz pictures. When the Video CD player is connected to a display with a different timebase to the coded disc material, some adjustments must be made to allow for the different number of lines on the display and the reconstructed picture. Two examples are shown in Figs. 3 and 4. The VCD chip can be programmed to position the reconstructed picture with respect to horizontal and vertical syncs anywhere on the display screen with a programmable `viewport' position. Figure 3 shows an MPEG SIF resolution picture (352 pixels by 288 lines) being displayed on an NTSC display having only 240 active display lines per field. In this event, the top and bottom 24 lines are not displayed.
1996 May 21
9
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
The second example, illustrated in Fig.4, is where a 240 active lines per field NTSC picture needs to be displayed on a 288 line PAL format display. The `missing' lines can be filled with a programmable border colour. High-resolution still pictures can be present on a Video CD disc.
SAA2510
In this event, the horizontal and vertical resolution of the reconstructed picture is double that of normal resolution (moving) pictures. In order to fit the picture in the available frame buffer DRAM, a data compression scheme is applied to the stored picture.
handbook, halfpage
reconstructed picture 352 not displayed
handbook, halfpage
display window 352 border = blank
24
reconstructed picture window
240 288
viewport
240 288
24
not displayed
MGE332
border = blank
MGE333
Fig.3
One field of a 625-line picture on a 525-line display.
Fig.4 525-line picture on a 625-line display.
1996 May 21
10
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
`Trickmode' implementation Compared with CD digital audio players, it is likely that Video CD players will need to offer additional functionality similar to VCRs. These features are commonly called `trickmodes'. Typically, the player will offer features such as still picture (freeze frame), scan forwards and backwards as well as slow motion replay. These features require a combination of CD servo control and Video CD decoder functions for effective implementation. The VCD chip provides high level command features to support these modes in order to minimize microcontroller time-critical software. STILL PICTURE DISPLAY This is implemented directly using a Pause command, causing the VCD chip to hold the displayed picture at the next frame update. SCAN FORWARD AND SCAN BACKWARDS There is no difference as far as the VCD chip is concerned. The controlling microcomputer must command the CD servo to execute a servo jump and re-synchronize. The VCD chip is then commanded to display the next I (Intra-coded) picture following re-acquisition of sector sync. SLOW-MOTION REPLAY A command is provided by the VCD chip, allowing a slow-motion `factor' in the range 2 to 8 to be selected. This is the factor by which replay will be slowed down. Because the rate of decoding of video sectors has been reduced, the video FIFO fills up. The block decoder is designed to automatically disable acquisition when the video FIFO fills in this way and an interrupt is generated. At this point, the next wanted sector (address) has been loaded into a register in the VCD chip. The controlling microcomputer then commands a CD servo jump to position on the disc just before the next desired sector, making allowance for re-synchronization by the servo and VCD chip. I2C-bus interface The VCD chip is programmed via the I2C-bus interface. The chip is a slave transceiver capable of operating at the maximum specified bus clock frequency of 400 kHz. It does not support the general call feature. One of two slave addresses can be used. The address is selected by the ASEL input pin. This bus provides access to the internal registers of the device. The bus is also used to write OSD slice data and 1996 May 21 11 Two and three byte sub-addressing S SLA S = START SLA = Slave address W = Write SUB_A = Sub-address W
SAA2510
to read data stored in three play-control sector buffers, which normally will be used to store Video CD data track information. This interface features a two or three byte sub-addressing scheme allowing access to any DRAM location. However, in normal use, only two byte sub-addressing is needed. An interrupt pin is available to signal a number of events so that the controlling processor does not need to poll VCD status registers. Input pin NDAV is used to signal that data on the block decoder input is not valid, e.g. during CD servo jumps. A complete memory map and list of registers will be included in a later version of this data sheet. I2C-bus slave address selection A6 0 Note 1. ASEL. The data transfer protocol is as follows: Two and three byte sub-addressing: first the device sub-address is transmitted, preceded by a START condition and the slave address: A5 0 A4 1 A3 1 A2 0 A1 1 A0 A0(1) R/W
SUB_A
The sub-address can be either 2 or 3 bytes. The 3-byte sub-address is used for DRAM random access. This is not used for normal operation. It exists only as a test mode. Since the Video CD IC is internally fully word (16 bits) oriented, the sub-address must always be an even address. If an odd-numbered address is given, the Video CD IC will not acknowledge this byte. For the sub-address, the least significant byte is sent first. The second sub-address byte contains 2 control bits.
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
Sub-address byte format MSB A7 A6 A5 A4 A3 A2 A1 LSB A0 MSB C1 C0 A13 A12 A11 A10
SAA2510
LSB A9 A8
When A0 is a `1', the address byte is not acknowledged (odd address). Explanation of control bits C0 = 0; 2-byte sub-address. C0 = 1; 3-byte sub-address. The next byte transmitted is also an address byte: 3-byte sub-address - most significant byte format MSB 0 0 0 A18 A17 A16 A15 LSB A14
I2C-bus transaction summary The following notation is used to describe bus transactions: S: START condition generated by bus master P: STOP condition generated by bus master A: Acknowledge bit generated by master or slave according to transaction type and stage N: Negative acknowledge; acknowledge bit is not set by bus master during last byte of a read SLA: 7-bit slave address generated by bus master W: R/W bit after slave address is set to write R: R/W bit after slave address is set to read SUB_N: Sub-address byte N (N = 0, 1 or 2); least significant address byte is SUB_0 D(M): A data byte transmitted by master or slave on the bus; D(0) is the first byte sent; as all transfers must be an even number of bytes, it follows that M must be odd.
C1 = 0; sub-address post increment enabled. After each transfer of 2 bytes, the address is automatically incremented by 2. C1 = 1; sub-address post increment disabled. The master will terminate a read action by NOT acknowledging the last read byte followed by a STOP condition.
Set 2-byte sub-address and write (M + 1) bytes S SLA W A SUB_0 A SUB_1 A D(0) A D(1) A to D(M) A P
Set 2-byte sub-address and read (M + 1) bytes S SLA W A SUB_0 A SUB_1 A S SLA R D(0) A D(1) A to D(M) N P
Set 3-byte sub-address and write (M + 1) bytes S SLA W A SUB_0 A SUB_1 A SUB_2 A D(0) A D(1) A to D(M) A P
Set 3-byte sub-address and read (M + 1) bytes S SLA WA SUB_0 A SUB_1 A SUB_2 A S SLA R A D(0) A D(1) A to D(M) N P
This addressing mode is valid only if sub-address auto incrementing is disabled. It is intended for fast polling of a status register.
1996 May 21
12
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
Byte-order within words LSB Word I2C-bus B15 B7 B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0 B7 B15 B6 B14 B5 B13 B4 B12 B3 B11
SAA2510
MSB B2 B10 B1 B9 B0 B8
For each transmitted word (read or written) the least significant byte is transmitted first. CHARACTERISTICS Tamb = -20 to +70 C; VDD5 = 4.5 to 5.5 V; VDD3 = 3.0 to 3.6 V; unless otherwise specified. SYMBOL Supplies VDD5 IDD5 VDD3 IDD3 IDD(tot) Digital inputs ALL INPUTS (EXCEPT RESET AND OSCILLATOR INPUTS) VIL VIH ILI Ci VIL VIH ILI Vhys Inputs/outputs SDA AND SCL (I2C-BUS DATA AND CLOCK) VIL VIH ILI Ci CL VOL VOL CLK27 VIL VIH 1996 May 21 LOW level input voltage HIGH level input voltage 13 -0.3 2.4 - - +0.8 V VDD + 0.5 V LOW level input voltage HIGH level input voltage input leakage current input capacitance load capacitance LOW level output voltage LOW level output voltage (IOL = 3.0 mA) (IOL = 6.0 mA) Vi = 0 to VDD -0.5 3 -10 - - 0 0 - - - - - - - +1.5 +10 10 400 0.4 0.6 V A pF pF V V VDD + 0.5 V LOW level input voltage HIGH level input voltage input leakage current input capacitance Vi = 0 to VDD -0.3 2 -10 - -0.3 3.5 Vi = 0 to VDD -10 1 - - - - - +0.8 +10 10 +2 +10 - V A pF VDD + 0.5 V supply voltage (5 V) range VDD5 supply current supply voltage (3 V) range VDD3 supply current total supply current 4.5 - 3 - - 5 tbf 3.3 tbf tbf 5.5 tbf 3.6 tbf tbf V mA V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
RESET INPUT: (SCHMITT INPUT) LOW level input voltage HIGH level input voltage input leakage current hysteresis voltage (VIH - VIL) V A V VDD + 0.5 V
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL ILI Ci VOL VOH tr tf VIL VIH ILI Ci CL VOL VOH tr tf Outputs
PARAMETER input leakage current input capacitance LOW level output voltage HIGH level output voltage input rise time input fall time
CONDITIONS Vi = 0 to VDD (IOL = 1.6 mA) (IOH = -0.2 mA) 0.6 to 2.6 V 0.6 to 2.6 V - 0
MIN. -10 - - - - - - - - - - - - - - -
TYP.
MAX. +10 10 0.4 VDD 4 4 +0.8 +10 10 30 0.4 VDD 10 10
UNIT A pF V V ns ns
2.6 - - -0.3 2
DR15 TO DR0 (DRAM DATA I/O) LOW level input voltage HIGH level input voltage input leakage current input capacitance load capacitance LOW level output voltage HIGH level output voltage output rise time output fall time (IOL = 1.6 mA) (IOH = -0.2 mA) 0.6 to 2.6 V; load = CL 0.6 to 2.6 V; load = CL Vi = 0 to VDD V A pF pF V V ns ns VDD + 0.5 V
-10 - - 0 2.4 3 3
RAS, CAS, W, A0 TO A8 (DRAM CONTROL AND ADDRESS LINES) VOL VOH CL tr tf VOL VOH CL tr tf VOL VOH CL tr tf VOL CL tr LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0.6 to 2.2 V; load = CL 0.6 to 2.2 V; load = CL (IOL = 1.6 mA) (IOH = -0.2 mA) 0.6 to 2.6 V; load = CL 0.6 to 2.6 V; load = CL (IOL = 1.6 mA) (IOH = -0.2 mA) 0.6 to 2.2 V; load = CL 0.6 to 2.2 V; load = CL (IOL = 1.6 mA) 0.6 to 2.2 V; load = CL 3 3 (IOL = 1.6 mA) (IOH = -0.2 mA) 0 2.4 - - - - - - - - - - - - - - - - - - 0.4 VDD 30 10 10 V V pF ns ns
Y0 TO Y7 (VIDEO OUTPUT Y BUS) LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0 2.4 - - - 0 2.4 - - 3 0.4 VDD 30 4 4 V V pF ns ns
UV0 TO UV7 (VIDEO OUTPUT UV BUS) LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0.4 VDD 30 10 10 V V pF ns ns
INT (OPEN DRAIN; INTERRUPT) LOW level output voltage load capacitance output rise time 0 - - 0.4 30 10 V pF ns
1996 May 21
14
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL tf VOL VOH CL tr tr ALL OTHER INPUTS VOL VOH CL tr tf
PARAMETER output fall time
CONDITIONS 0.6 to 2.2 V; load = CL (IOL = 10 mA) (IOH = -10 mA) 0.8 V to (VDD5 - 0.8 V); load = CL 0.8 V to (VDD5 - 0.8 V); load = CL (IOL = 1.6 mA) (IOH = -0.2 mA) 0.6 to 2.6 V; load = CL 0.6 to 2.6 V; load = CL - 0
MIN. - - - - - -
TYP.
MAX. 10
UNIT ns
EBUOUT (IEC 958 OUT) LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 1 VDD 50 10 10 V V pF ns ns VDD5-1 - - -
LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time
0 2.4 - - -
- - - - -
0.4 VDD 50 30 30
V V pF ns ns
I2S input/output timing; (Fig.5) INPUT TIMING fclk tclkH tclkL tsu th1 OUTPUT TIMING fclk tclkH th2 td output clock frequency output clock HIGH period hold time (DAOUT, WSOUT) output delay time (DAOUT, WSOUT) - 166 195 - 2.118 - - - - - - 147 MHz ns ns ns input clock frequency input clock HIGH period input clock LOW period set-up time (DAIN, EFIN, WSIN) hold time DAIN, EFIN, WSIN) - 166 166 95 0 2.118 - - - - - - - - - MHz ns ns ns ns
I2C-bus input/output timing (Fig.6) 100 kHz CLOCK FREQUENCY fclk tLOW tHIGH tSU;DAT tHD;DAT tSU;STO clock frequency clock LOW period period data set-up time data hold time set-up time clock HIGH to STOP 0 4.7 4 250 0 4.7 - - - - - - 100 - - - - - kHz s s ns ns s
1996 May 21
15
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL tBUF tHD;STA tSU;STA tr tf fclk tLOW tHIGH tSU;DAT tHD;DAT tSU;STO tBUF tHD;STA tSU;STA tr tf
PARAMETER set-up time STOP to START START hold time set-up time clock rising edge to START rise time (SDA and SCL) fall time (SDA and SCL)
CONDITIONS
MIN. 4.7 4 4.7 - - - - - - - - - - - - - - - -
TYP. - - -
MAX.
UNIT s s s ns ns
VILmin to VIHmax VILmin to VIHmax
50 50
1000 300
400 kHz CLOCK FREQUENCY clock frequency clock LOW period period data set-up time data hold time set-up time clock HIGH to STOP set-up time STOP to START START hold time set-up time clock rising edge to START rise time (SDA and SCL) fall time (SDA and SCL) VILmin to VIHmax VILmin to VIHmax 0 1.3 0.6 100 0 0.6 1.3 0.6 0.6 50 50 400 - - - - - - - - 300 300 kHz s s ns ns s s s s ns ns
Video Output Timing (Figs. 7 and 8) 16-BIT VIDEO OUTPUT MODE tsu th2 tsu th1 set-up time (CREF, HREF, UV and Y valid to CLK27) hold time (CLK27 to CREF, HREF, UV and Y invalid) set-up time (UV and Y valid to CREF rising edge) hold time (CREF rising edge to UV and Y invalid) 10 3 6 10 - - - - - - - - ns ns ns ns
8-BIT VIDEO OUTPUT MODE tsu th2 set-up time (HREF and Y valid to CLK27) hold time (CLK27 to HREF and Y invalid) 7 5 - - - - ns ns
DRAM Timing (Fig.9) tCYC tRP tCSH tRCD 1996 May 21 cycle time RAS pre-charge time CAS hold time RAS to CAS delay time 16 130 50 70 20 - - - - - - - - ns ns ns ns
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL tCAS tPC tCP tRSH tCRP tASR tRAH tASC tCAH tRCS tRCH tRRH tWCS tWCH tDS tDH tCAC tRAC
PARAMETER CAS pulse width LOW page mode cycle time CAS pre-charge time RAS hold time after CAS CAS to RAS pre-charge time row address set-up time row address hold time column address set-up time column address hold time read command set-up time read command hold time (CAS) read command hold time (RAN) write command set-up time write command hold time data-in set-up time data-in hold time read access time (CAS) read access time (RAS)
CONDITIONS
MIN. 20 50 10 20 15 0 10 0 15 0 0 0 0 15 0 15 - - - - - - - - - - - - - - - - - - - -
TYP. - - - - - - - - - - - - - - - -
MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
20 70
Crystal oscillators 40 MHz SYSTEM CLOCK OSCILLATOR Vosc(p-p) Gv Gm Ci Cfb fOSC f Vosc(p-p) GV Gm Ci oscillation amplitude (peak-to-peak) small signal voltage gain mutual conductance input capacitance feedback capacitance oscillation frequency frequency tolerance - - tbf - - - - - - tbf - tbf tbf - - tbf 40 - tbf tbf - - - - - tbf - - - - - - tbf mA/V pF mA/V pF pF MHz ppm V
27 MHz SYSTEM CLOCK OSCILLATOR oscillation amplitude (peak-to-peak) small signal voltage gain mutual conductance input capacitance V
1996 May 21
17
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL Cfb fosc f
PARAMETER feedback capacitance oscillation frequency frequency tolerance
CONDITIONS - - -
MIN.
TYP. tbf 27 - - - -
MAX.
UNIT pF MHz ppm
handbook, full pagewidth
tclkH I2S bit clock CLKIN or CLKOUT td I2S data and word select outputs DAOUT, WSOUT tsu I2S data, word select and error flags inputs DAIN, WSIN, EFIN
MGE327
tclkL
th
th
Fig.5 I2S input/output timing.
handbook, full pagewidth
tr tHIGH tLOW
tf
SCL
tSU; STA tHD; STA SDA
tSU; DAT
tHD; DAT
tSU;STO
tBUF
MGE328
Fig.6 I2C-bus timing.
1996 May 21
18
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
handbook, full pagewidth 27 MHz clock
(CLK27) th1 tsu CREF tsu1 HREF th1 tsu2 th2 th2 V0 (Cr0) V718
U0 (Cb0)
Y0 pixel #0 CSYNC (1)
Y1
Y719 pixel #719
MGE329
Timing applies to CLK27 when programmed as an input or an output of the SAA2510. (1) CSYNC (HIGH-to-LOW) to first sample and HREF (LOW-to-HIGH) = 264.5/244.5 CLK27 periods (625 lines/525 lines mode).
Fig.7 16-bit video output mode timing.
27 MHz clock handbook, full pagewidth (CLK27) tsu HREF th1 Y bus output Cb Y pixel #0 Cr Y719 pixel #719
MGE330
th2
Fig.8 8-bit video CCIR656 output mode timing.
1996 May 21
19
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
handbook, full pagewidth
tRP
tCYC tRSH
RAS tCSH tPC CAS tRCD tRAH tCAS tASC tASR ADDRESS tCAH tCP tCRP
tRRH tRCS tRCH
W tCAC DRAM data out tRAC tWCS W tDH tWCH READ CYCLE
tDS VCD data to DRAM
WRITE CYCLE
MGE331
Fig.9 DRAM timing.
1996 May 21
20
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
APPLICATION INFORMATION
SAA2510
handbook, full pagewidth
40 MHz crystal
0V
Sys_osc_0 EBU input EBUIN AUDIOCLK CLIN DAIN WSIN ESIN COMPACT DISC MECHANISM AND DECODER 16 9 4 Mbit DRAM
Sys_osc_1 EBUOUT
EBU INTERFACE
CLOUT DAOUT WSOUT AUDIO DAC
Audio L, R
DR0 to DR15 A0 to A8 CASN RASN W
HREF VSYNC
CVBS DIGITAL VIDEO ENCODER VP0 to 7 CREF LLC +5 V e.g.: SAA7185 I2C-bus Y, C
SAA2510
UV0 to 7 Y0 to 7 CREF
8 8
ASEL I2C-bus SDA SCL RESET MICROCONTROLLER AND USER INTERFACE
CLK27 CDIR
Vid_osc_0 27 MHz crystal
NDAV INTN DRAMON TEST1, 2 2 0V
MGE326
0V
Vid_osc_1
VCD power supply pins not shown.
Fig.10 Application diagram; 16-bit video output mode.
1996 May 21
21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SAA2510
SOT317-1
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1 (A 3) Lp bp 100 1 wM D HD ZD B vM B 30 vM A 31 detail X L
wM pin 1 index
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.3 A1 0.36 0.10 A2 2.87 2.57 A3 0.25 bp 0.40 0.25 c 0.25 0.13 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1996 May 21
22
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA2510
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 May 21
23
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA2510
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 May 21
24
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
NOTES
SAA2510
1996 May 21
25
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
NOTES
SAA2510
1996 May 21
26
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
NOTES
SAA2510
1996 May 21
27
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02) 805 4455, Fax. (02) 805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. (01) 60 101-1256, Fax. (01) 60 101-1250 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. (172) 200 733, Fax. (172) 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. (359) 2 689 211, Fax. (359) 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: see South America China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. (852) 2319 7888, Fax. (852) 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032) 88 2636, Fax. (031) 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358) 0-615 800, Fax. (358) 0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01) 4099 6161, Fax. (01) 4099 6427 Germany: P.O. Box 10 51 40, 20035 HAMBURG, Tel. (040) 23 53 60, Fax. (040) 23 53 63 00 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01) 4894 339/4894 911, Fax. (01) 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, BOMBAY 400 018 Tel. (022) 4938 541, Fax. (022) 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01) 7640 000, Fax. (01) 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. (03) 645 04 44, Fax. (03) 648 10 07 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. (0039) 2 6752 2531, Fax. (0039) 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. (03) 3740 5130, Fax. (03) 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02) 709-1412, Fax. (02) 709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03) 750 5214, Fax. (03) 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. 9-5(800) 234-7831, Fax. (708) 296-8556 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. (040) 2783749, Fax. (040) 2788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09) 849-4160, Fax. (09) 849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022) 74 8000, Fax. (022) 74 8341 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. (022) 612 2831, Fax. (022) 612 2327 Portugal: see Spain Romania: see Italy Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65) 350 2000, Fax. (65) 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011) 470-5911, Fax. (011) 470-5494 South America: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011) 821-2333, Fax. (011) 829-1849 Spain: Balmes 22, 08007 BARCELONA, Tel. (03) 301 6312, Fax. (03) 301 4107 Sweden: Kottbygatan 7, Akalla. S-16485 STOCKHOLM, Tel. (0) 8-632 2000, Fax. (0) 8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01) 488 2211, Fax. (01) 481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. (66) 2 745-4090, Fax. (66) 2 398-0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0212) 279 2770, Fax. (0212) 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181) 730-5000, Fax. (0181) 754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800) 234-7381, Fax. (708) 296-8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. (381) 11 825 344, Fax. (359) 211 635 777
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31-40-2724825 SCDS48 (c) Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/01/pp28 Document order number: Date of release: 1996 May 21 9397 750 00851

▲Up To Search▲

Price & Availability of SAA2510

	To Download SAA2510 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .